
u-eject:     file format elf64-littleaarch64


Disassembly of section .init:

0000000000400648 <_init>:
  400648:	a9bf7bfd 	stp	x29, x30, [sp, #-16]!
  40064c:	910003fd 	mov	x29, sp
  400650:	9400004a 	bl	400778 <call_weak_fn>
  400654:	a8c17bfd 	ldp	x29, x30, [sp], #16
  400658:	d65f03c0 	ret

Disassembly of section .plt:

0000000000400660 <.plt>:
  400660:	a9bf7bf0 	stp	x16, x30, [sp, #-16]!
  400664:	90000090 	adrp	x16, 410000 <__FRAME_END__+0xf4c8>
  400668:	f947fe11 	ldr	x17, [x16, #4088]
  40066c:	913fe210 	add	x16, x16, #0xff8
  400670:	d61f0220 	br	x17
  400674:	d503201f 	nop
  400678:	d503201f 	nop
  40067c:	d503201f 	nop

0000000000400680 <open@plt>:
  400680:	b0000090 	adrp	x16, 411000 <open@GLIBC_2.17>
  400684:	f9400211 	ldr	x17, [x16]
  400688:	91000210 	add	x16, x16, #0x0
  40068c:	d61f0220 	br	x17

0000000000400690 <__libc_start_main@plt>:
  400690:	b0000090 	adrp	x16, 411000 <open@GLIBC_2.17>
  400694:	f9400611 	ldr	x17, [x16, #8]
  400698:	91002210 	add	x16, x16, #0x8
  40069c:	d61f0220 	br	x17

00000000004006a0 <memset@plt>:
  4006a0:	b0000090 	adrp	x16, 411000 <open@GLIBC_2.17>
  4006a4:	f9400a11 	ldr	x17, [x16, #16]
  4006a8:	91004210 	add	x16, x16, #0x10
  4006ac:	d61f0220 	br	x17

00000000004006b0 <strdup@plt>:
  4006b0:	b0000090 	adrp	x16, 411000 <open@GLIBC_2.17>
  4006b4:	f9400e11 	ldr	x17, [x16, #24]
  4006b8:	91006210 	add	x16, x16, #0x18
  4006bc:	d61f0220 	br	x17

00000000004006c0 <close@plt>:
  4006c0:	b0000090 	adrp	x16, 411000 <open@GLIBC_2.17>
  4006c4:	f9401211 	ldr	x17, [x16, #32]
  4006c8:	91008210 	add	x16, x16, #0x20
  4006cc:	d61f0220 	br	x17

00000000004006d0 <__gmon_start__@plt>:
  4006d0:	b0000090 	adrp	x16, 411000 <open@GLIBC_2.17>
  4006d4:	f9401611 	ldr	x17, [x16, #40]
  4006d8:	9100a210 	add	x16, x16, #0x28
  4006dc:	d61f0220 	br	x17

00000000004006e0 <abort@plt>:
  4006e0:	b0000090 	adrp	x16, 411000 <open@GLIBC_2.17>
  4006e4:	f9401a11 	ldr	x17, [x16, #48]
  4006e8:	9100c210 	add	x16, x16, #0x30
  4006ec:	d61f0220 	br	x17

00000000004006f0 <puts@plt>:
  4006f0:	b0000090 	adrp	x16, 411000 <open@GLIBC_2.17>
  4006f4:	f9401e11 	ldr	x17, [x16, #56]
  4006f8:	9100e210 	add	x16, x16, #0x38
  4006fc:	d61f0220 	br	x17

0000000000400700 <free@plt>:
  400700:	b0000090 	adrp	x16, 411000 <open@GLIBC_2.17>
  400704:	f9402211 	ldr	x17, [x16, #64]
  400708:	91010210 	add	x16, x16, #0x40
  40070c:	d61f0220 	br	x17

0000000000400710 <printf@plt>:
  400710:	b0000090 	adrp	x16, 411000 <open@GLIBC_2.17>
  400714:	f9402611 	ldr	x17, [x16, #72]
  400718:	91012210 	add	x16, x16, #0x48
  40071c:	d61f0220 	br	x17

0000000000400720 <ioctl@plt>:
  400720:	b0000090 	adrp	x16, 411000 <open@GLIBC_2.17>
  400724:	f9402a11 	ldr	x17, [x16, #80]
  400728:	91014210 	add	x16, x16, #0x50
  40072c:	d61f0220 	br	x17

Disassembly of section .text:

0000000000400730 <_start>:
  400730:	d280001d 	mov	x29, #0x0                   	// #0
  400734:	d280001e 	mov	x30, #0x0                   	// #0
  400738:	aa0003e5 	mov	x5, x0
  40073c:	f94003e1 	ldr	x1, [sp]
  400740:	910023e2 	add	x2, sp, #0x8
  400744:	910003e6 	mov	x6, sp
  400748:	580000c0 	ldr	x0, 400760 <_start+0x30>
  40074c:	580000e3 	ldr	x3, 400768 <_start+0x38>
  400750:	58000104 	ldr	x4, 400770 <_start+0x40>
  400754:	97ffffcf 	bl	400690 <__libc_start_main@plt>
  400758:	97ffffe2 	bl	4006e0 <abort@plt>
  40075c:	00000000 	.inst	0x00000000 ; undefined
  400760:	0040082c 	.word	0x0040082c
  400764:	00000000 	.word	0x00000000
  400768:	00400a30 	.word	0x00400a30
  40076c:	00000000 	.word	0x00000000
  400770:	00400ab0 	.word	0x00400ab0
  400774:	00000000 	.word	0x00000000

0000000000400778 <call_weak_fn>:
  400778:	90000080 	adrp	x0, 410000 <__FRAME_END__+0xf4c8>
  40077c:	f947f000 	ldr	x0, [x0, #4064]
  400780:	b4000040 	cbz	x0, 400788 <call_weak_fn+0x10>
  400784:	17ffffd3 	b	4006d0 <__gmon_start__@plt>
  400788:	d65f03c0 	ret
  40078c:	00000000 	.inst	0x00000000 ; undefined

0000000000400790 <deregister_tm_clones>:
  400790:	b0000080 	adrp	x0, 411000 <open@GLIBC_2.17>
  400794:	9101a000 	add	x0, x0, #0x68
  400798:	b0000081 	adrp	x1, 411000 <open@GLIBC_2.17>
  40079c:	9101a021 	add	x1, x1, #0x68
  4007a0:	eb00003f 	cmp	x1, x0
  4007a4:	540000a0 	b.eq	4007b8 <deregister_tm_clones+0x28>  // b.none
  4007a8:	90000001 	adrp	x1, 400000 <_init-0x648>
  4007ac:	f9456821 	ldr	x1, [x1, #2768]
  4007b0:	b4000041 	cbz	x1, 4007b8 <deregister_tm_clones+0x28>
  4007b4:	d61f0020 	br	x1
  4007b8:	d65f03c0 	ret
  4007bc:	d503201f 	nop

00000000004007c0 <register_tm_clones>:
  4007c0:	b0000080 	adrp	x0, 411000 <open@GLIBC_2.17>
  4007c4:	9101a000 	add	x0, x0, #0x68
  4007c8:	b0000081 	adrp	x1, 411000 <open@GLIBC_2.17>
  4007cc:	9101a021 	add	x1, x1, #0x68
  4007d0:	cb000021 	sub	x1, x1, x0
  4007d4:	9343fc21 	asr	x1, x1, #3
  4007d8:	8b41fc21 	add	x1, x1, x1, lsr #63
  4007dc:	9341fc21 	asr	x1, x1, #1
  4007e0:	b40000a1 	cbz	x1, 4007f4 <register_tm_clones+0x34>
  4007e4:	90000002 	adrp	x2, 400000 <_init-0x648>
  4007e8:	f9456c42 	ldr	x2, [x2, #2776]
  4007ec:	b4000042 	cbz	x2, 4007f4 <register_tm_clones+0x34>
  4007f0:	d61f0040 	br	x2
  4007f4:	d65f03c0 	ret

00000000004007f8 <__do_global_dtors_aux>:
  4007f8:	a9be7bfd 	stp	x29, x30, [sp, #-32]!
  4007fc:	910003fd 	mov	x29, sp
  400800:	f9000bf3 	str	x19, [sp, #16]
  400804:	b0000093 	adrp	x19, 411000 <open@GLIBC_2.17>
  400808:	3941a260 	ldrb	w0, [x19, #104]
  40080c:	35000080 	cbnz	w0, 40081c <__do_global_dtors_aux+0x24>
  400810:	97ffffe0 	bl	400790 <deregister_tm_clones>
  400814:	52800020 	mov	w0, #0x1                   	// #1
  400818:	3901a260 	strb	w0, [x19, #104]
  40081c:	f9400bf3 	ldr	x19, [sp, #16]
  400820:	a8c27bfd 	ldp	x29, x30, [sp], #32
  400824:	d65f03c0 	ret

0000000000400828 <frame_dummy>:
  400828:	17ffffe6 	b	4007c0 <register_tm_clones>

000000000040082c <main>:
  40082c:	a9b37bfd 	stp	x29, x30, [sp, #-208]!
  400830:	910003fd 	mov	x29, sp
  400834:	b9001fa0 	str	w0, [x29, #28]
  400838:	f9000ba1 	str	x1, [x29, #16]
  40083c:	12800000 	mov	w0, #0xffffffff            	// #-1
  400840:	b900cfa0 	str	w0, [x29, #204]
  400844:	528003c0 	mov	w0, #0x1e                  	// #30
  400848:	390163a0 	strb	w0, [x29, #88]
  40084c:	390167bf 	strb	wzr, [x29, #89]
  400850:	39016bbf 	strb	wzr, [x29, #90]
  400854:	39016fbf 	strb	wzr, [x29, #91]
  400858:	390173bf 	strb	wzr, [x29, #92]
  40085c:	390177bf 	strb	wzr, [x29, #93]
  400860:	90000000 	adrp	x0, 400000 <_init-0x648>
  400864:	912ca001 	add	x1, x0, #0xb28
  400868:	910143a0 	add	x0, x29, #0x50
  40086c:	b9400022 	ldr	w2, [x1]
  400870:	b9000002 	str	w2, [x0]
  400874:	b8402021 	ldur	w1, [x1, #2]
  400878:	b8002001 	stur	w1, [x0, #2]
  40087c:	90000000 	adrp	x0, 400000 <_init-0x648>
  400880:	912cc001 	add	x1, x0, #0xb30
  400884:	910123a0 	add	x0, x29, #0x48
  400888:	b9400022 	ldr	w2, [x1]
  40088c:	b9000002 	str	w2, [x0]
  400890:	b8402021 	ldur	w1, [x1, #2]
  400894:	b8002001 	stur	w1, [x0, #2]
  400898:	b9401fa0 	ldr	w0, [x29, #28]
  40089c:	7100081f 	cmp	w0, #0x2
  4008a0:	540000c0 	b.eq	4008b8 <main+0x8c>  // b.none
  4008a4:	90000000 	adrp	x0, 400000 <_init-0x648>
  4008a8:	912b8000 	add	x0, x0, #0xae0
  4008ac:	97ffff91 	bl	4006f0 <puts@plt>
  4008b0:	12800000 	mov	w0, #0xffffffff            	// #-1
  4008b4:	1400005c 	b	400a24 <main+0x1f8>
  4008b8:	f9400ba0 	ldr	x0, [x29, #16]
  4008bc:	91002000 	add	x0, x0, #0x8
  4008c0:	f9400000 	ldr	x0, [x0]
  4008c4:	97ffff7b 	bl	4006b0 <strdup@plt>
  4008c8:	f90063a0 	str	x0, [x29, #192]
  4008cc:	90000000 	adrp	x0, 400000 <_init-0x648>
  4008d0:	912c0000 	add	x0, x0, #0xb00
  4008d4:	f94063a1 	ldr	x1, [x29, #192]
  4008d8:	97ffff8e 	bl	400710 <printf@plt>
  4008dc:	52810001 	mov	w1, #0x800                 	// #2048
  4008e0:	f94063a0 	ldr	x0, [x29, #192]
  4008e4:	97ffff67 	bl	400680 <open@plt>
  4008e8:	b900cfa0 	str	w0, [x29, #204]
  4008ec:	b940cfa0 	ldr	w0, [x29, #204]
  4008f0:	7100001f 	cmp	w0, #0x0
  4008f4:	5400012a 	b.ge	400918 <main+0xec>  // b.tcont
  4008f8:	90000000 	adrp	x0, 400000 <_init-0x648>
  4008fc:	912c4000 	add	x0, x0, #0xb10
  400900:	f94063a1 	ldr	x1, [x29, #192]
  400904:	97ffff83 	bl	400710 <printf@plt>
  400908:	f94063a0 	ldr	x0, [x29, #192]
  40090c:	97ffff7d 	bl	400700 <free@plt>
  400910:	12800000 	mov	w0, #0xffffffff            	// #-1
  400914:	14000044 	b	400a24 <main+0x1f8>
  400918:	910183a0 	add	x0, x29, #0x60
  40091c:	d2800b02 	mov	x2, #0x58                  	// #88
  400920:	52800001 	mov	w1, #0x0                   	// #0
  400924:	97ffff5f 	bl	4006a0 <memset@plt>
  400928:	52800a60 	mov	w0, #0x53                  	// #83
  40092c:	b90063a0 	str	w0, [x29, #96]
  400930:	528000c0 	mov	w0, #0x6                   	// #6
  400934:	3901a3a0 	strb	w0, [x29, #104]
  400938:	52800400 	mov	w0, #0x20                  	// #32
  40093c:	3901a7a0 	strb	w0, [x29, #105]
  400940:	12800000 	mov	w0, #0xffffffff            	// #-1
  400944:	b90067a0 	str	w0, [x29, #100]
  400948:	b9006fbf 	str	wzr, [x29, #108]
  40094c:	910103a0 	add	x0, x29, #0x40
  400950:	f9003ba0 	str	x0, [x29, #112]
  400954:	910083a0 	add	x0, x29, #0x20
  400958:	f90043a0 	str	x0, [x29, #128]
  40095c:	5284e200 	mov	w0, #0x2710                	// #10000
  400960:	b9008ba0 	str	w0, [x29, #136]
  400964:	910163a0 	add	x0, x29, #0x58
  400968:	f9003fa0 	str	x0, [x29, #120]
  40096c:	910183a0 	add	x0, x29, #0x60
  400970:	aa0003e2 	mov	x2, x0
  400974:	d28450a1 	mov	x1, #0x2285                	// #8837
  400978:	b940cfa0 	ldr	w0, [x29, #204]
  40097c:	97ffff69 	bl	400720 <ioctl@plt>
  400980:	b900bfa0 	str	w0, [x29, #188]
  400984:	b940bfa0 	ldr	w0, [x29, #188]
  400988:	7100001f 	cmp	w0, #0x0
  40098c:	5400038b 	b.lt	4009fc <main+0x1d0>  // b.tstop
  400990:	910143a0 	add	x0, x29, #0x50
  400994:	f9003fa0 	str	x0, [x29, #120]
  400998:	910183a0 	add	x0, x29, #0x60
  40099c:	aa0003e2 	mov	x2, x0
  4009a0:	d28450a1 	mov	x1, #0x2285                	// #8837
  4009a4:	b940cfa0 	ldr	w0, [x29, #204]
  4009a8:	97ffff5e 	bl	400720 <ioctl@plt>
  4009ac:	b900bfa0 	str	w0, [x29, #188]
  4009b0:	b940bfa0 	ldr	w0, [x29, #188]
  4009b4:	7100001f 	cmp	w0, #0x0
  4009b8:	5400026b 	b.lt	400a04 <main+0x1d8>  // b.tstop
  4009bc:	910123a0 	add	x0, x29, #0x48
  4009c0:	f9003fa0 	str	x0, [x29, #120]
  4009c4:	910183a0 	add	x0, x29, #0x60
  4009c8:	aa0003e2 	mov	x2, x0
  4009cc:	d28450a1 	mov	x1, #0x2285                	// #8837
  4009d0:	b940cfa0 	ldr	w0, [x29, #204]
  4009d4:	97ffff53 	bl	400720 <ioctl@plt>
  4009d8:	b900bfa0 	str	w0, [x29, #188]
  4009dc:	b940bfa0 	ldr	w0, [x29, #188]
  4009e0:	7100001f 	cmp	w0, #0x0
  4009e4:	5400014b 	b.lt	400a0c <main+0x1e0>  // b.tstop
  4009e8:	d2824be1 	mov	x1, #0x125f                	// #4703
  4009ec:	b940cfa0 	ldr	w0, [x29, #204]
  4009f0:	97ffff4c 	bl	400720 <ioctl@plt>
  4009f4:	b900bfa0 	str	w0, [x29, #188]
  4009f8:	14000006 	b	400a10 <main+0x1e4>
  4009fc:	d503201f 	nop
  400a00:	14000004 	b	400a10 <main+0x1e4>
  400a04:	d503201f 	nop
  400a08:	14000002 	b	400a10 <main+0x1e4>
  400a0c:	d503201f 	nop
  400a10:	b940cfa0 	ldr	w0, [x29, #204]
  400a14:	97ffff2b 	bl	4006c0 <close@plt>
  400a18:	f94063a0 	ldr	x0, [x29, #192]
  400a1c:	97ffff39 	bl	400700 <free@plt>
  400a20:	52800000 	mov	w0, #0x0                   	// #0
  400a24:	a8cd7bfd 	ldp	x29, x30, [sp], #208
  400a28:	d65f03c0 	ret
  400a2c:	00000000 	.inst	0x00000000 ; undefined

0000000000400a30 <__libc_csu_init>:
  400a30:	a9bc7bfd 	stp	x29, x30, [sp, #-64]!
  400a34:	910003fd 	mov	x29, sp
  400a38:	a901d7f4 	stp	x20, x21, [sp, #24]
  400a3c:	90000094 	adrp	x20, 410000 <__FRAME_END__+0xf4c8>
  400a40:	90000095 	adrp	x21, 410000 <__FRAME_END__+0xf4c8>
  400a44:	91374294 	add	x20, x20, #0xdd0
  400a48:	913722b5 	add	x21, x21, #0xdc8
  400a4c:	a902dff6 	stp	x22, x23, [sp, #40]
  400a50:	cb150294 	sub	x20, x20, x21
  400a54:	f9001ff8 	str	x24, [sp, #56]
  400a58:	2a0003f6 	mov	w22, w0
  400a5c:	aa0103f7 	mov	x23, x1
  400a60:	9343fe94 	asr	x20, x20, #3
  400a64:	aa0203f8 	mov	x24, x2
  400a68:	97fffef8 	bl	400648 <_init>
  400a6c:	b4000194 	cbz	x20, 400a9c <__libc_csu_init+0x6c>
  400a70:	f9000bb3 	str	x19, [x29, #16]
  400a74:	d2800013 	mov	x19, #0x0                   	// #0
  400a78:	f8737aa3 	ldr	x3, [x21, x19, lsl #3]
  400a7c:	aa1803e2 	mov	x2, x24
  400a80:	aa1703e1 	mov	x1, x23
  400a84:	2a1603e0 	mov	w0, w22
  400a88:	91000673 	add	x19, x19, #0x1
  400a8c:	d63f0060 	blr	x3
  400a90:	eb13029f 	cmp	x20, x19
  400a94:	54ffff21 	b.ne	400a78 <__libc_csu_init+0x48>  // b.any
  400a98:	f9400bb3 	ldr	x19, [x29, #16]
  400a9c:	a941d7f4 	ldp	x20, x21, [sp, #24]
  400aa0:	a942dff6 	ldp	x22, x23, [sp, #40]
  400aa4:	f9401ff8 	ldr	x24, [sp, #56]
  400aa8:	a8c47bfd 	ldp	x29, x30, [sp], #64
  400aac:	d65f03c0 	ret

0000000000400ab0 <__libc_csu_fini>:
  400ab0:	d65f03c0 	ret

Disassembly of section .fini:

0000000000400ab4 <_fini>:
  400ab4:	a9bf7bfd 	stp	x29, x30, [sp, #-16]!
  400ab8:	910003fd 	mov	x29, sp
  400abc:	a8c17bfd 	ldp	x29, x30, [sp], #16
  400ac0:	d65f03c0 	ret
